The invention relates generally to Integrated Circuit (IC) cards or smart cards used in processing transactions involving goods and services. Smart cards are plastic cards having microprocessor and memory circuits attached to the front or back side that connect to electrical contacts located on a front side of the card. The circuits are activated and data accessed from the card by inserting the card into a reader device that makes connections to the electrical contacts. More particularly, the invention relates to a device and method for connecting a smart card to smart card reader devices that have different interface characteristics. Furthermore, the invention relates to a novel method and device for generating an internal clock signal that is synchronized by an externally applied signal.
Smart cards are a class of data cards. Data cards used in processing transactions are either passive or active in nature. Passive data cards include traditional credit, debit and ATM cards that make use of stored data on a magnetic strip on the back of the card. When a transaction is processed using a passive data card, transaction verification is generally required via a reader device connected to a remote computer over a telephone network. During a transaction, data may be written and read from the magnetic strip. Active data cards or smart cards make use of processor and memory circuits embedded on the card that are activated when the card is connected to a reader device. Since smart cards may contain the intelligence required to complete a transaction, the transaction may be completed locally without resorting to a telephone connection to a remote transaction verification facility. In addition to storing data related to the owner""s account such as identification number and account balance, the circuits also contain encryption for security purposes. Smart cards are used in many applications, including Subscriber Identification Module (SIM) in Global System for Mobile (GSM) telephones, TV satellite receivers, banking, health care programs, parking and highway toll payment, etc. Smart cards are expected to find increasingly wider application, eventually replacing magnetic strip type data cards.
The basic smart card standard is the International Standard ISO 7816, which provides detailed requirements for the physical, electrical, mechanical, and application programming interface for IC cards with contacts. In particular, International Standard ISO 7816-1 Physical Characteristics, International Standard 7816-2 Dimension and Location of the Contacts, and International Standard ISO 7816-3 Electronic Signals and Transmission Protocols are incorporated herein by reference. This standard provides for a serial interface connection to the smart card. In a great majority of cases, these cards are used in a reader connected to a computer. The reader contains electronic circuits that enable communication between the card and the computer. The reader is connected to a computer by means of a serial or parallel port on the computer.
The Universal Serial Bus (USB) has recently become firmly established and has gained wide acceptance in the Personal Computer (PC) marketplace. The USB was developed in response to a need for a standard interface that extends the concept of xe2x80x9cplug and playxe2x80x9d to devices external to a PC, and enables users to install and remove external peripheral devices without having to open the PC case or to remove power from the PC. The USB provides a low-cost, half-duplex serial interface that is easy to use and readily expandable. The USB also supplies up to 500 mA of current at 5 volts to interconnected devices. The USB is currently defined by the Universal Serial Bus Specification written and controlled by USB Implementers Forum, Inc., a non-profit corporation founded by the group of companies that developed the USB Specification. In particular, Chapter 5 USB Data Flow Model, Chapter 7 Electrical, and Chapter 8 Protocol Layer of Universal Serial Bus Specification are incorporated herein by reference. The increasingly widespread use of the USB in computers has led smart card reader manufacturers to develop USB interfaces for connection of their products to computers to complement the existing serial and parallel interfaces. However, because of the differences between the serial interface defined by ISO 7816 and the serial interface defined by the USB specification, smart cards have not been directly compatible with the USB specification. And different card reader configurations have been required due to incompatibility constraints between the various computer interface standards.
The USB Specification version 1.1 defines two theoretical data transfer speed rates. A low-speed at 1.5 megabits per second and a full-speed at 12 megabits per second are provided. A high-speed data transfer rate greater than 480 megabits per second is anticipated for high data throughput application such as video or mass storage. The present invention preferably makes use of the low-speed implementation of packet transactions. When taking into account the different overheads and protocols, the effective USB low speed data rate varies between 50 kilobits per second and 400 kilobits per second depending of the available bandwidth. This data rate outperforms the data rate achieved by use of the ISO 7816 Standard. The higher data rate makes possible a reduction in smart card customizing time, and increases possible applications.
A hub provides USB attachment points. Attachment points are referred to as ports. The host has an embedded hub called the root hub that provides one or more attachment points. A USB device provides additional functionality to the host and is connected to one of the ports of any hub. The host, embedded in a PC, masters the USB. Each device reacts in a master-slave relationship. Every transaction starts by a host request. The USB does not have any dedicated clock signal lines. Each hub and each USB device has its own reference clock. The hub supports both low speed and full speed data signaling rates. The hub clock generator uses a crystal to provide the xc2x10.25% timing accuracy required for full speed transactions. A low speed device clock generator tolerance of xc2x11.5% is compatible with the use of a cheaper resonator. All USB transactions, downstream and upstream, begin with a Synchronization Pattern (SP) signal that allows the device and the hub clocks to lock in phase. Because of the lack of space and limited contact pin availability, neither a crystal nor a resonator is practical solutions for clocking USB circuitry on a smart card.
For the foregoing reasons, there is a need to provide a smart card with a capability for local clock generation using the SP and Packet Identifier (PID) signals, without the use of crystals, resonators or other components external to an integrated circuit. There is a further need to connect a smart card to an USB port without the need for any interposing electronic circuitry.
The present invention is directed towards a device and method for providing a smart card with the capability of supporting the serial interface defined by the USB specification without adding any additional complexity to the smart card or reader.
The present invention is also directed towards a device and method for generating a USB device clock signal synchronized with a USB signal, without the need for a crystal or resonator. Furthermore, the present invention is also directed towards a device and method for connecting a smart card to a USB port with a simple connector without the need for any interposing electronic circuitry.
The present invention relates to a physical link between a USB port and a smart card. It describes a solution to generate a USB low speed device clock without using any external components.
When a hub sends information to an Integrated Circuit Module (ICM) on a smart card, the ICM is in a reception mode. This is referred to as a downstream transaction. When the ICM sends information to the hub, the hub is in reception mode. This is referred to as an upstream transaction. In a last communication combination, the hub and the ICM are both in a reception mode, which comprises an idle state. During data transmission, DP and DM signal lines carry differential signals such that when DP is at xe2x80x9c1xe2x80x9d, DM is at xe2x80x9c0xe2x80x9d and vice versa. The voltage slew rate on DP and DM is limited to 3.6 Volt/75 ns. These two characteristics minimize radiated Electromagnetic Interference (EMI) by the device.
The passage from one transmitter to the next occurs in the following sequence. A current transmitter reports an End Of Packet (EOP) and sets the USB in the J state (DM at xe2x80x9c1xe2x80x9d and DP at xe2x80x9c0xe2x80x9d) for one bit duration. The DM and DP signal lines are then caused to float, where none of the transmitters are active, and pull-down and pull-up devices define voltages on the DP and DM signal lines. When the next transmitter sets the bus in the J state for one bit duration, a new transmission starts with a new SP signal.
A host request starts with a SP followed by a PID. SP and PID transmit known bit patterns. SP signals are used in downstream and upstream transactions to lock a device or hub reception clock in phase with a transmission clock. PID signals are used in downstream and upstream transactions to identify the packet. A differential receiver whose inputs are connected to the signals DP and DM shapes an RXD signal.
The present invention uses downstream SP and PID signals sent by the hub to generate a device clock signal CLK1X with a nominal frequency of 1.5 MHz and a precision better than xc2x11.5% and, at the same time, to lock the device clock signal CLK1X phase with the downstream RXD signal phase.
The present invention contained within a device has a free running clock signal CLKOSC. A period of the CLKOSC signal is known within xc2x130%, but has stability of better than 0.1% over a short period of time (1 millisecond). The first downstream Token Packet received by a device incorporating the present invention calibrates a CLK1X signal period at better than xc2x11.5% using CLKOSC signal and locks the CLK1X signal in phase with the downstream received signal RXD. Once the calibrations are completed, the device incorporating the present invention can receive or send data. Every other downstream SP and PID received by a device containing the present invention starts a new calibration procedure for the device clock signal period and its phase, furthermore every other downstream data toggling signal received outside SP and PID resynchronizes the phase of the device clock signal CLK1X. This compensates for Initial inaccuracy, temperature sensitivity and long term drift of CLKOSC.
A method having features of the present invention comprises a method for generating a local clock signal in a device using Universal Serial Bus downstream signals DP and DM, comprising receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals, counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal, dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal, and generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T. The step of generating the local clock signal may comprise counting the number of the free-running high frequency clock cycles T to generate a period of the local clock signal, and initializing the counting step when there is a data toggling in the received downstream bit serial signal for locking in phase the generated local clock with the received downstream bit serial signal. The step of generating the local clock signal may further comprise updating the period of the local clock signal when a known received downstream bit serial pattern is recognized. The known number of bit periods S of the received downstream bit-serial signal may be eight. The method may further comprise generating the free-running high frequency clock signal with a ring oscillator. The step of generating the free-running high frequency clock signal with a ring oscillator further may comprise generating an even number of signals V having a period of the free-running high frequency clock signal and the phase shifted of 360xc2x0/V. The even number of signals V may be eight. The method may be implemented in an integrated circuit module. The integrated circuit module may be positioned on a smart card. The local clock signal may be phase locked with the downstream bit serial signal at least once every seven bit periods of the downstream bit serial signal by the use of bit-stuffing. The counting step may be performed during a period of time when the downstream bit serial signal comprises a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet. The known received downstream bit serial pattern may comprise a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet. The method may further comprise a step for determining if T is within predefined limits. The local clock signal may be used to sample the USB received downstream serial bit data and to time the USB transmitted upstream serial bit data.
In an alternate embodiment of the invention, a device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, comprises means for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals, means for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal, means for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal, and means for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T. The means for generating the local clock signal may comprise means for counting the number of the free-running high frequency clock cycles T to generate a period of the local clock signal, and means for initializing the counting step when there is a data toggling in the received downstream bit serial signal for locking in phase the generated local clock with the received downstream bit serial signal. The means for generating the local clock signal may further comprise means for updating the period of the local clock signal when a known received downstream bit serial pattern is recognized. The known number of bit periods S of the received downstream bit-serial signal may be eight. The means for generating the free-running high frequency clock signal may be a ring oscillator. The means for generating the free-running high frequency clock signal with a ring oscillator may further comprise means for generating an even number of signals V having a period of the free-running high frequency clock signal and the phase shifted of 360xc2x0/V. The even number of signals V may be eight. The circuit may be implemented in an integrated circuit module. The integrated circuit module may be positioned on a smart card. The local clock signal may be phase locked with the downstream bit serial signal at least once every seven bit periods of the downstream bit serial signal by the use of bit-stuffing. The counting means may be performed during a period of time when the downstream bit serial signal comprises a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet. The known received downstream bit serial pattern may comprise a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet. The circuit may further comprise a means for determining if T is within predefined limits. The local clock signal may be used to sample the USB received downstream serial bit data and to time the USB transmitted upstream serial bit data.
In another alternate embodiment of the invention, a device containing a circuit for generating a local clock signal using Universal Serial Bus downstream signals DP and DM, may comprise a differential receiver for receiving the USB downstream differential signals DP and DM and generating a downstream bit-serial signal from the USB downstream signals, a first counter connected to the bit serial signal for counting a number of cycles R of a free-running high frequency clock signal contained within a known number of bit periods S of the received downstream bit-serial signal, a divider circuit for dividing the counted number of cycles R of the free-running high frequency clock signal by the known number of bit periods S of the received downstream bit-serial signal for determining a resultant number of the free-running high frequency clock cycles T contained within a single bit period of the received downstream bit-serial signal, and a second counter for generating a local clock signal having a period equal to the number of free-running high frequency clock cycles T. The second counter may be initialized by data toggling in the received downstream bit serial signal. The free-running high frequency clock signal may be generated by an eight phase ring oscillator. The first counter may be enabled during a period of time when the downstream bit serial signal comprises a Sync byte and a PID Setup byte of a USB Token Packet and Data Packet.